法国国家信息与自动化研究院（INRIA Sophia-Antipolis） Robert de Simone
Robert de Simone 教授的报告摘要
Title: Formal model engineering for embedded applications and many-core architectures
Abstract: There is a definite trend towards parallelism at all levels in modern computing architectures. But compilation of embedded applications onto such platforms remains quite far from automatic, at least if efficiency is to be achieved. Steps in this direction would involve:
- extracting the potential concurrency from the application models (which is often large in the embedded field);
- specifying an explicit model of the parallel architecture, including relevant non-functional aspects (timing, power consumption,...);
- efficiently mapping the former virtual concurrency onto the latter actual parallelism, while routing communications on the interconnect fabric.
A formal instance of this framework will be presented, with both its theoretical and engineering sides. A number of pre-existing formal methods and models will be introduced, selected for their relevance to this main goal. Data Flow Process Networks, Synchronous Languages, Nested Loop programs will be considered in great details, together with the relevant scheduling/routing schemes they promote. Mathematical properties of these models will particularly be stressed. Relevant scope is also considered an issue, since predictability and regularity such as demanded by these theories is not always met on rather chaotic implementations
Robert de Simone教授简介:
Robert de Simone is currently Senior Researcher at INRIA Sophia-Antipolis (FRANCE). He is scientific leader of the Aoste team, a research group dedicated to modeling and analysis of real-time embedded systems. His main domains of interest in the past were Concurrency Theory and Process Algebras, formal semantics, automatic verification and model-checking, with an emphasis on Synchronous Reactive Systems and the Esterel language. More recently he was involved in the design of the MARTE UML profile for Real-Time Embedded systems, and the use of model-driven engineering techniques based on formal models to help with the efficient mapping of embedded applications onto many core architecture platforms and systems-on-chip.
Title:From Multi-Cores to Clouds, Challengers and Opportunities with ProActive Parallel Suite
Abstract ：This presentation will give an overview of issues at hand when accelerating demanding applications with Multi-Cores, Clusters, Servers and Clouds. With ProActive Parallel Suite, an Open Source library for parallel, distributed, and concurrent computing, allowing to showcase Interactive and graphical GUI and tools, it will detail how one can reduce administration costs and hardware expenditures by virtualizing the hardware resources: monitor and control all resources in a uniform manner, appropriately schedule the distribution of task flows and applications execution over the available resources. Then, the presentation explains how to manage actual VMs in such an infrastructure, including operations such as Start, Stop, Clone, Destroy. Overall, it is shown how simple it is now to dynamically aggregate and manage many different kinds of enterprise resources (Desktop, Server, Cluster, VMs), and seamlessly upon demand, to extend them with Public Clouds (e.g. Amazon EC2).
The talk will also feature stunning Use Cases: Large Scale Processing of Genomic Sequencing, acceleration of Financial Valuations and of the Analysis of Web Server Logs in an SOA context. When appropriate, the actual cost of running partially of fully onto Public Clouds is presented.
Dr. Yu Feng is working as project-coordinator and engineer expert in INRIA. With background in Engineering and Mathematics, she holds a Ph.D in Dublin City University (DCU), Ireland in 1997. She has been very active in both industry and academic after Ph.D studies. Commercially, Dr. Feng has extensive experience in international product development with a number of multi-national corporations in Europe, i.e. Microsoft, Novell, Canon, Amadeus; her roles in this sphere extend from software development through to project management. She has joined the Oasis team of INRIA Sophia since Oct 2006, and has been working on several FP6/FP7 and Stic-Asia joint projects, related to Parallel Computing, Distributed system, Grid/Cloud Computing and Applications